industrial temperature range IDT74LVC823A 3.3v cmos 9-bit bus-interface flip-flop 1 january 2004 industrial temperature range the idt logo is a registered trademark of integrated device technology, inc. ? 2004 integrated device technology, inc. dsc-4608/2 features: ? 0.5 micron cmos technology ? esd > 2000v per mil-std-883, method 3015; > 200v using machine model (c = 200pf, r = 0) ?v cc = 3.3v 0.3v, normal range ?v cc = 2.7v to 3.6v, extended range ? cmos power levels (0.4 w typ. static) ? rail-to-rail output swing for increased noise margin ? all inputs, outputs, and i/o are 5v tolerant ? supports hot insertion ? available in ssop, qsop, and tssop packages functional block diagram drive features: ? high output drivers: 24ma ? reduced system switching noise IDT74LVC823A description: the lvc823a 9-bit bus-interface flip-flop is built using advanced dual metal cmos technology. the lvc823a device is designed specifically for driving highly capacitive or relatively low-impedance loads. the device is particularly suitable for implementing wider buffer registers, i/o ports, bidirectional bus drivers with parity, and working registers. with the clock-enable ( clken ) input low, the nine d-type edge-triggered flip-flops enter data on the low-to-high transitions of the clock. taking clken high disables the clock buffer, latching the outputs. this device has noninverting data (d) inputs. taking the clear ( clr ) input low causes the nine q outputs to go low, independently of the clock. a buffered output-enable ( oe ) input can be used to place the nine outputs in either a normal logic state (high or low logic levels) or a high-impedance state. oe does not affect internal operations of the latch. previously stored data can be retained or new data can be entered while the outputs are in the high-impedance state. the lvc823a has been designed with a 24ma output driver. this driver is capable of driving a moderate to heavy load while maintaining speed performance. to ensure the high-impedance state during power up or power down, oe should be tied to v cc through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. inputs can be driven from either 3.3v or 5v devices. this feature allows the use of this device as a translator in a mixed 3.3v/5v system environment. 3.3v cmos 9-bit bus-interface flip-flop with 3-state outputs and 5 volt tolerant i/o oe c 1 1 d clken 1 d to eight other channels 1 14 2 23 1 q clr 11 13 clk r applications: ? 3.3v high speed systems ? 3.3v and lower voltage computing systems
industrial temperature range 2 IDT74LVC823A 3.3v cmos 9-bit bus-interface flip-flop symbol description max unit v term terminal voltage with respect to gnd ?0.5 to +6.5 v t stg storage temperature ?65 to +150 c i out dc output current ?50 to +50 ma i ik continuous clamp current, ?50 ma i ok v i < 0 or v o < 0 i cc continuous current through each 100 ma i ss v cc or gnd absolute maximum ratings (1) note: 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. pin configuration ssop/ qsop/ tssop top view note: 1. as applicable to the device type. symbol parameter (1) conditions typ. max. unit c in input capacitance v in = 0v 4.5 6 pf c out output capacitance v out = 0v 5.5 8 pf c i/o i/o port capacitance v in = 0v 6.5 8 pf capacitance (t a = +25c, f = 1.0mhz) 2 3 1 1 d v cc 20 19 18 5 q 4 q 6 q 2 q 1 q 3 q 15 8 q 9 q 16 9 10 8 d 7 q 23 22 24 21 17 oe 5 6 6 d 7 4 d 5 d 4 2 d 3 d 8 9 d 7 d 13 clken clk 14 11 12 clr gnd function table (each flip-flop) (1) notes: 1. h = high voltage level l = low voltage level x = don?t care z = high impedance = low-to-high transition 2. output level before indicated steady-state input conditions were established. inputs outputs oe clr clken clk xd xq llxxx l lhl hh lhl ll lhhxx q (2) hxxxx z pin names description oe output enable input (active low) clk clock input clken clock enable input (active low) clr clear input (active low) xd data inputs x q data outputs pin description
industrial temperature range IDT74LVC823A 3.3v cmos 9-bit bus-interface flip-flop 3 symbol parameter test conditions min. typ. (1) max. unit v ih input high voltage level v cc = 2.3v to 2.7v 1.7 ? ? v v cc = 2.7v to 3.6v 2 ? ? v il input low voltage level v cc = 2.3v to 2.7v ? ? 0.7 v v cc = 2.7v to 3.6v ? ? 0.8 i ih input leakage current v cc = 3.6v v i = 0 to 5.5v ? ? 5a i il i ozh high impedance output current v cc = 3.6v v o = 0 to 5.5v ? ? 10 a i ozl (3-state output pins) i off input/output power off leakage v cc = 0v, v in or v o 5.5v ? ? 50 a v ik clamp diode voltage v cc = 2.3v, i in = ?18ma ? ?0.7 ?1.2 v v h input hysteresis v cc = 3.3v ? 100 ? mv i ccl quiescent power supply current v cc = 3.6v v in = gnd or v cc ?? 10a i cch i ccz 3.6 v in 5.5v (2) ?? 10 ? i cc quiescent power supply current one input at v cc - 0.6v, other inputs at v cc or gnd ? ? 500 a variation dc electrical characteristics over operating range following conditions apply unless otherwise specified: operating condition: t a = ?40c to +85c notes: 1. typical values are at v cc = 3.3v, +25c ambient. 2. this applies in the disabled state only. note: 1. v ih and v il must be within the min. or max. range shown in the dc electrical characteristics over operating range table for the appropriat e v cc range. t a = ? 40c to + 85c. output drive characteristics symbol parameter test conditions (1) min. max. unit v oh output high voltage v cc = 2.3v to 3.6v i oh = ? 0.1ma v cc ? 0.2 ? v v cc = 2.3v i oh = ? 6ma 2 ? v cc = 2.3v i oh = ? 12ma 1.7 ? v cc = 2.7v 2.2 ? v cc = 3v 2.4 ? v cc = 3v i oh = ? 24ma 2.2 ? v ol output low voltage v cc = 2.3v to 3.6v i ol = 0.1ma ? 0.2 v v cc = 2.3v i ol = 6ma ? 0.4 i ol = 12ma ? 0.7 v cc = 2.7v i ol = 12ma ? 0.4 v cc = 3v i ol = 24ma ? 0.55
industrial temperature range 4 IDT74LVC823A 3.3v cmos 9-bit bus-interface flip-flop switching characteristics (1) v cc = 2.7v v cc = 3.3v 0.3v symbol parameter min. max. min. max. unit f max 150 ? 150 ? m h z t plh propagation delay ? 8.9 1.4 8 ns t phl clk to xq t phl propagation delay ? 8.8 2.5 7.9 ns clr to xq t pzh output enable time ? 8.3 1.6 7.2 ns t pzl oe to xq t phz output disable time ? 7.1 1.1 6 ns t plz oe to xq t w pulse duration, clr low 3.3 ? 3.3 ? ns t w pulse duration, clk high or low 3.3 ? 3.3 ? ns t su set-up time, clr inactive before clk 1? 1?ns t su set-up time, data before clk 1.3 ? 1.3 ? ns t su set-up time, clken low before clk 1.8 ? 1.8 ? ns t h hold time, data after clk 2? 2?ns t h hold time, clken low after clk 1.3 ? 1.3 ? ns t sk (o) output skew (2) ?? ? 1ns notes: 1. see test circuits and waveforms. t a = ? 40c to + 85c. 2. skew between any two outputs of the same package and switching in the same direction. operating characteristics, v cc = 3.3v 0.3v, t a = 25c symbol parameter test conditions typical unit c pd power dissipation capacitance per flip-flop outputs enabled c l = 0pf, f = 10mhz 59 pf c pd power dissipation capacitance per flip-flop outputs disabled 46
industrial temperature range IDT74LVC823A 3.3v cmos 9-bit bus-interface flip-flop 5 open v load gnd v cc pulse generator d.u.t. 500 ? 500 ? c l r t v in v out (1, 2) lvc link input v ih 0v v oh v ol t plh1 t sk (x) output 1 output 2 t phl1 t sk (x) t plh2 t phl2 v t v t v oh v t v ol t sk (x) = t plh2 - t plh1 or t phl2 - t phl1 lvc link same phase input transition opposite phase input transition 0v 0v v oh v ol t plh t phl t phl t plh output v ih v t v t v ih v t lvc link data input 0v 0v 0v 0v t rem timing input asynchronous control synchronous control t su t h t su t h v ih v t v ih v t v ih v t v ih v t lvc link low-high-low pulse high-low-high pulse v t t w v t lvc link control input t plz 0v output normally low t pzh 0v switch v load output normally high enable disable switch gnd t phz 0v v ol+ v lz v oh v t v t t pzl v load/2 v load/2 v ih v t v ol v oh- v hz lvc link test circuits and waveforms propagation delay test circuit for all outputs enable and disable times set-up, hold, and release times notes: 1. for t sk (o) output1 and output2 are any two outputs. 2. for t sk (b) output1 and output2 are in the same bank. definitions: c l = load capacitance: includes jig and probe capacitance. r t = termination resistance: should be equal to z out of the pulse generator. notes: 1. pulse generator for all pulses: rate 10mhz; t f 2.5ns; t r 2.5ns. 2. pulse generator for all pulses: rate 10mhz; t f 2ns; t r 2ns. output skew - t sk ( x ) pulse width note: 1. diagram shown for input control enable-low and input control disable-high. symbol v cc (1) = 3.3v0.3v v cc (1) = 2.7v v cc (2) = 2.5v0.2v unit v load 6 6 2 x vcc v v ih 2.7 2.7 vcc v v t 1.5 1.5 vcc / 2 v v lz 300 300 150 mv v hz 300 300 150 mv c l 50 50 30 pf test conditions switch position test switch open drain disable low v load enable low disable high gnd enable high all other tests open
industrial temperature range 6 IDT74LVC823A 3.3v cmos 9-bit bus-interface flip-flop ordering information corporate headquarters for sales: for tech support: 2975 stender way 800-345-7015 or 408-727-6116 logichelp@idt.com santa clara, ca 95054 fax: 408-492-8674 (408) 654-6459 www.idt.com idt xx lvc xxxx xx package device type temp. range py q pg 74 shrink small outline package quarter size small outline package thin shrink small outline package 9-bit bus-interface flip-flop with 3-state outputs, 24ma ?40c to +85c x bus-hold 823a no bus-hold blank
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